http://smartech.gatech.edu/handle/1853/79 Reports published by researchers associated with the Center Search the Channel search http://smartech.gatech.edu/simple-search http://smartech.gatech.edu/handle/1853/27247 Title: A Petri Net Approach to Analysis and Composition of Web Services <br/> <br/>Authors: Xiong, PengCheng; Fan, YuShun; Zhou, MengChu <br/> <br/>Abstract: Business Process Execution Language for Web Services (BPEL) is becoming the industrial standard for modeling web service-based business processes. Behavioral compatibility for web service composition is one of the most important topics. The commonly used reachability exploration method focuses on verifying deadlock-freeness. When this property is violated, the states and traces in the reachability graph only give clues to re-design the composition. The process must then repeat itself until no deadlock is found. In this paper, multiple web services interaction is modeled with a Petri net called Composition net (C-net for short). The problem of behavioral compatibility among web services is hence transformed into the deadlock structure problem of a C-net. If services are incompatible, a policy based on appending additional information channels is proposed. It is proved that it can offer a good solution that can be mapped back into the BPEL models automatically. Wed, 29 Oct 2008 22:58:59 GMT http://smartech.gatech.edu/handle/1853/27246 Title: Translating GPU Binaries to Tiered SIMD Architectures with Ocelot <br/> <br/>Authors: Diamos, Gregory; Kerr, Andrew; Kesavan, Mukil <br/> <br/>Abstract: Parallel Thread Execution ISA (PTX) is a virtual instruction set used by NVIDIA GPUs that explicitly expresses hierarchical MIMD and SIMD style parallelism in an application. In such a programming model, the programmer and compiler are left with the not trivial, but not impossible, task of composing applications from parallel algorithms and data structures. Once this has been accomplished, even simple architectures with low hardware complexity can easily exploit the parallelism in an application. With these applications in mind, this paper presents Ocelot, a binary translation framework designed to allow architectures other than NVIDIA GPUs to leverage the parallelism in PTX programs. Specifically, we show how (i) the PTX thread hierarchy can be mapped to many-core architectures, (ii) translation techniques can be used to hide memory latency, and (iii) GPU data structures can be efficiently emulated or mapped to native equivalents. We describe the low level implementation of our translator, ending with a case study detailing the complete translation process from PTX to SPU assembly used by the IBM Cell Processor. Wed, 29 Oct 2008 22:58:59 GMT http://smartech.gatech.edu/handle/1853/27232 Title: Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching <br/> <br/>Authors: Woo, Dong Hyuk; Fryman, Joshua B.; Knies, Allan D.; Lee, Hsien-Hsin Sean <br/> <br/>Abstract: Heterogeneous multi-core processors have emerged as an energy- and area-efficient architectural solution to improving performance for domain-specific applications such as those with a plethora of data-level parallelism. These processors typically contain a large number of small, compute-centric cores for acceleration while keeping one or two high-performance ILP cores on the die to guarantee single-thread performance. Although a major portion of the transistors are occupied by the acceleration cores, these resources will sit idle when running unparallelized legacy codes or the sequential parts of an application. To address this under-utilization issue, in this paper, we introduce Chameleon, a flexible heterogeneous multi-core architecture to virtualize these resources for enhancing memory performance when running sequential programs. The Chameleon architecture can dynamically virtualize the idle acceleration cores into a last-level cache, a data prefetcher, or a hybrid between these two techniques. In addition, Chameleon can operate in an adaptive mode which dynamically configures the acceleration cores between the hybrid mode and the prefetch-only mode by monitoring the effectiveness of Chameleon caching scheme. In our evaluation using SPEC2006 benchmark suite, different levels of performance improvements were achieved in different modes for different applications. In the case of the adaptive mode, Chameleon improves the performance of SPECint06 and SPECfp06 by 33% and 22% on average. When considering only memory-intensive applications, Chameleon improves the system performance by 53% and 33%. Mon, 29 Oct 2007 22:58:59 GMT http://smartech.gatech.edu/handle/1853/27231 Title: A HyperTransport-Enabled Global Memory Model For Improved Memory Efficiency <br/> <br/>Authors: Young, Jeffrey; Yalamanchili, Sudhakar; Silla, Federico; Duato, José <br/> <br/>Abstract: Modern and emerging data centers are presenting unprecedented demands in terms of cost and energy consumption, far outpacing architectural advances related to economies of scale. Consequently, blade designs exhibit significant cost and power inefficiencies, particularly in the memory system. For example, we observe that modern blades are often overprovisioned to accommodate peak memory demand which rarely occurs concurrently across blades. With memory often accounting for 20% to 40% of the total system power [1], this approach is not sustainable. Concurrently, HyperTransport in concert with new high-bandwidth commodity interconnects can provide low-latency sharing of memory across blades. This paper provides a HyperTransport-enabled solution for seamless, efficient sharing of memory across blades in a data center, leading to significant power and cost savings. Specifically, we propose a new global address space model called the Dynamic Partitioned Global Address Space (DPGAS) model that extends previous concepts for Non-Uniform Memory Access (NUMA) and partitioned global address spaces (PGAS). The DPGAS model relies on HyperTransport’s low-latency characteristics to enable new techniques for efficient sharing of memory across data center blades. This paper presents the DPGAS model, describes HyperTransport-based hardware support for the model, and assesses this model’s power and cost impact on memory intensive applications. Overall, we find that cost savings can range from 4% to 26% with power reductions ranging from 2% to 25% across a variety of fixed application configurations using server consolidation and memory throttling. The HyperTransport implementation enables these savings with an additional node latency cost of 1,690 ns latency per remote 64 byte cache line access across the blade-to-blade interconnect. Mon, 29 Oct 2007 22:58:59 GMT