• Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Architecture 

      Lee, Jaekyu; Li, Si; Kim, Hyesoon; Yalamanchili, Sudhakar (Georgia Institute of Technology, 2012)
      Future chip multiprocessors (CMP) will only grow in core count and diversity in terms of frequency, power consumption, and resource distribution. Incorporating a GPU architecture into CMP, which is more efficient with ...
    • The PARADE Environment for Visualizing Parallel Program Executions: A Progress Report 

      Stasko, John T. (Georgia Institute of Technology, 1995)
      This report describes the current status of the PARADE visualization environment. PARADE supports the design and implementation of software visualizations of parallel and distributed programs. It contains primary components ...
    • Visualizing the Execution of Threads-based Parallel Programs 

      Stasko, John T.; Zhao, Qiang Alex (Georgia Institute of Technology, 1995)
      One popular model of concurrent computing is threads-based parallel programming on a shared memory parallel computer. A variety of different vendors and machines provide such capabilities, and support for threads programming ...