Microarchitecture-Aware Physical Planning for Deep Submicron Technology
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The main objective of this thesis is to develop a new design paradigm that combines microarchitecture design and circuit design with physical design for deep submicron technology. For deep submicron technology, wire delay will be the bottleneck for high performance microarchitecture design. Given the location information, inter-module latency can be calculated and hence, performance of the system can be estimated. In this thesis, we present a novel microarchitectural floorplanning that can help computer architects tackle the wire delay problem early in the microarchitecture design stage. We show that by employing microarchitectural floorplanning up to 40\% performance gain can be achieved. We also extend the framework to include three dimensional integrated circuit (3D-IC). 3D-IC is a new integration technique that is also introduced to address the wire delay issue in deep submicron technology. By combining microarchitectural floorplanning with 3D-IC, we show that wire delay impact can be reduced substantially. We also show that not only the module location, but also the module size can impact the performance. Adaptive search engine is introduced to identify the right module size. Using our adaptive search engine, we show that the system can identify good module sizes that help improve the performance with a shorter run-time than the limited runtime brute force search. Our microarchitecture-aware physical planning assumes that the target clock period can be achieved by inserting more flip-flops into the system. Inserting flip-flops along the wires can make the system meet the timing constraints without violating correctness of the circuit on that path because the function of the wire is to transfer signal from one location to another. However, inserting the flip-flop along the paths that consist of gates cannot guarantee the correctness of that path. A circuit optimization technique that allows flip-flop insertion along circuit path is called retiming. In this dissertation, We show that retiming can be used to achieve target clock period in microprocessor design. With the same target clock period, power reduction technique can be combined with retiming to help reduce the power consumption. We show that up to 34% power reduction can be achieved without timing violation. Furthermore, to tackle the problem of process variation in deep submicron, we also propose a modified retiming that can tolerate errors from statistical timing computation. We show that our statistical retiming algorithm provides close results to Monte-Carlo simulation results.