Power Distribution in Gigascale Integration (GSI)
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The main objective of this thesis is to develop models for the power distribution network of high performance gigascale chips. The two main concerns in distributing power in a chip are voltage drop and electromigration-induced reliability failures. The voltage drop on the power distribution network is due to IR-drop and simultaneous switching noise. IR-drop is the voltage drop due to current passing through the resistances of the power distribution network. Simultaneous switching noise is due to varying current passing through the inductances of the power distribution network. Compact physical models are derived for the IR-drop and electromigration for different types of packages. These chip-package co-design models enable designers in the early stages of the design to estimate the on-chip interconnect resources, and also to choose type and size of the package required for power distribution. Modeling of the simultaneous switching noise requires the simulation of a large circuit with thousands of inductances. The main obstacle challenging the simulation of a simultaneous switching noise circuit model is the computing resources required to solve the dense inductance matrix. In this work, a new relative inductance matrix is introduced to solve massively coupled RLC interconnects. It is proven that the analysis using this method is accurate for a wide frequency range and all configurations. Using the new inductance matrix makes the circuit simulations significantly faster without losing accuracy.