• Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package 

      Wong, C. P.; Kang, E. T.; Tay, Andrew A. O.; Wong, E. H.; Swaminathan, Madhavan; Iyer, Mahadevan K.; Rotaru, Mihai D.; Tummala, Rao R.; Doraiswami, Ravi; Ang, Simon S.; Kripesh, V. (Georgia Institute of TechnologyInstitute of Electrical and Electronics Engineers, Inc., New York, 2004-05)
      According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 μm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data ...