• Correlation of Flip Chip Underfill Process Parameters and Material Properties with In-Process Stress Generation 

      Wong, C. P.; Palaniappan, Prema; Baldwin, Daniel F.; Selman, Paul J.; Wu, Jiali (Georgia Institute of TechnologyInstitute of Electrical and Electronics Engineers, Inc., New York, 1999-01)
      Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, ...
    • Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill 

      Lee, Sangil; Yim, Myung Jin; Master, Raj N.; Wong, C. P.; Baldwin, Daniel F. (Georgia Institute of TechnologyInstitute of Electrical and Electronics Engineers, 2009-04)
      The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications, presents challenges for flip ...
    • Void Formation Study of Flip Chip in Package Using No-Flow Underfill 

      Lee, Sangil; Yim, Myung Jin; Master, Raj N.; Wong, C. P.; Baldwin, Daniel F. (Georgia Institute of TechnologyInstitute of Electrical and Electronics Engineers, Inc., 2008-10)
      The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical ...