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dc.contributor.authorWong, C. P.
dc.contributor.authorPalaniappan, Prema
dc.contributor.authorBaldwin, Daniel F.
dc.contributor.authorSelman, Paul J.
dc.contributor.authorWu, Jiali
dc.date.accessioned2006-08-21T13:20:19Z
dc.date.available2006-08-21T13:20:19Z
dc.date.issued1999-01
dc.identifier.citationIEEE Transactions on Electronics Packaging Manufacturing, Vol. 22, no. 1, January 1999, 53-62en
dc.identifier.urihttp://hdl.handle.net/1853/11427
dc.description©1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en
dc.description.abstractElectronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing.en
dc.format.extent1301459 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen
dc.publisherGeorgia Institute of Technologyen
dc.subjectDirect chip attachen
dc.subjectElectronics manufacturingen
dc.subjectElectronics packagingen
dc.subjectFlip-chip devicesen
dc.subjectMicroelectronicsen
dc.titleCorrelation of Flip Chip Underfill Process Parameters and Material Properties with In-Process Stress Generationen
dc.typeArticleen
dc.publisher.originalInstitute of Electrical and Electronics Engineers, Inc., New York


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