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dc.contributor.authorWong, C. P.
dc.contributor.authorKang, E. T.
dc.contributor.authorTay, Andrew A. O.
dc.contributor.authorWong, E. H.
dc.contributor.authorSwaminathan, Madhavan
dc.contributor.authorIyer, Mahadevan K.
dc.contributor.authorRotaru, Mihai D.
dc.contributor.authorTummala, Rao R.
dc.contributor.authorDoraiswami, Ravi
dc.contributor.authorAng, Simon S.
dc.contributor.authorKripesh, V.
dc.date.accessioned2006-08-28T14:52:58Z
dc.date.available2006-08-28T14:52:58Z
dc.date.issued2004-05
dc.identifier.citationIEEE Transactions on Advanced Packaging, Vol. 27, no. 2, May 2004, 413-425en
dc.identifier.urihttp://hdl.handle.net/1853/11434
dc.description©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en
dc.description.abstractAccording to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 μm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-μm pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final “optimum” design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with coefficient of thermal expansion of 10 ppm/K or lower.en
dc.format.extent1153777 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen
dc.publisherGeorgia Institute of Technologyen
dc.subjectAssemblingen
dc.subjectIntegrated circuit interconnectionsen
dc.subjectIntegrated circuit modellingen
dc.subjectIntegrated circuit packagingen
dc.subjectIntegrated circuit reliabilityen
dc.subjectThermal expansionen
dc.titleNext Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Packageen
dc.typeArticleen
dc.publisher.originalInstitute of Electrical and Electronics Engineers, Inc., New York


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