Efficient Alternate Test Generation for RF Transceiver Architectures

Abstract

The production testing cost of modern wireless communication systems, especially basestation units, is estimated to be as high as 30-40 percent of their manufacturing cost and is increasing with system complexity, high levels of device integration and scaling of CMOS process technology and operating frequencies. The major production testing challenges for RF transceivers are: (a) the high cost of automated test development because of system-level simulation difficulties and the large simulation times involved, (b) the high cost of using high-end, communication protocol-aware RF test instrumentation, and (c) lack of external test access to RF circuits embedded inside integrated transceivers. Consequently, there exists a need for developing efficient design-for-test methodologies and non-invasive system-level test techniques for wireless transceivers to reduce their test cost. This dissertation is focused towards development of new system-level alternate test methodologies for RF transceiver architectures. The research proposes using non-invasive testing techniques for RF subsystems and digital-compatible built-in testing techniques for baseband and intermediate frequency (IF) analog circuits. The objectives of this research are: (a) to develop automatic test stimulus generation algorithms that allow accurate determination of targeted RF system-level test specification values using behavioral modeling and simulation techniques, (b) to develop RF transceiver test techniques that allow testing of embedded RF systems with limited test access, while reducing the test time for complex RF and baseband system-level performance metrics (b) to significantly reduce the test instrumentation overhead for testing complex frequency-domain and modulation-domain system specifications. The feasibility and the cost benefits of using the proposed alternate test approaches have been demonstrated using 900 MHz and 1575 MHz transceiver prototypes.