Space–Parallel Network Simulations Using Ghosts

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1853/13162

Title: Space–Parallel Network Simulations Using Ghosts
Author: Riley, George F. ; Jaafar, Talal Mohamed ; Fujimoto, Richard M. ; Ammar, Mostafa H. (Mostafa Hamed)
Abstract: We discuss an approach for creating a federated network simulation that eases the burdens on the simulator user that typically arise from more traditional methods for defining space-parallel simulations. Previous approaches have difficulties that arise from the need for global topology knowledge when forwarding simulated packets between the federates. In all but the simplest cases, proper packet forwarding decisions between federates requires routing tables of size O(mn) (m is the number of nodes modeled in a particular simulator instance, and n is the total number of network nodes in the entire topology) in order to determine how packets should be routed between federates. Further, the benefits of the well-known NIx-Vector routing approach cannot be fully achieved without global knowledge of the overall topology. We seek to overcome these difficulties by utilizing a topology partitioning methodology that uses Ghost Nodes. A ghost node is a simulator object in a federate that represents a simulated network node that is spatially assigned to some other federate, and thus that other federate is responsible for maintaining all state associated with the node. However, ghost nodes do retain topology connectivity information with other nodes, allowing all federate in a space-parallel simulation to obtain a global picture of the network topology. We show with experimental results that the memory overhead associated with the ghosts is minimal relative to the overall memory footprint of the simulation.
Description: ©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. Presented at 18th Workshop on Parallel and Distributed Simulation (PADS 04), 2004
Type: Proceedings
URI: http://hdl.handle.net/1853/13162
Date: 2004-05
Contributor: Georgia Institute of Technology. School of Electrical and Computer Engineering
Georgia Institute of Technology. College of Computing
Publisher: Georgia Institute of Technology
Institute of Electrical and Electronics Engineers, Inc., New York
Subject: Computational complexity
Computer networks
Digital simulation
Network topology
Packet switching
Parallel processing

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