A parallelism, instruction throughput, and cycle time model of computer architectures

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1853/13279

Title: A parallelism, instruction throughput, and cycle time model of computer architectures
Author: Taha, Tarek M.
Type: Dissertation
URI: http://hdl.handle.net/1853/13279
Date: 2002-12
Publisher: Georgia Institute of Technology
Subject: Computer architecture
Microprocessors Design and construction
Department: Electrical and Computer Engineering
Advisor: D. Scott Wills
Degree: Ph.D.

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