A parallel digital interconnect test methodology for multi-chip module substrate networks

Please use this identifier to cite or link to this item: http://hdl.handle.net/1853/13847

Title:	A parallel digital interconnect test methodology for multi-chip module substrate networks
Author:	Newman, Kimberly Eileen
Type:	Dissertation
URI:	http://hdl.handle.net/1853/13847
Date:	1999-05
Publisher:	Georgia Institute of Technology
Subject:	Multichip modules (Microelectronics) Testing Parallel processing (Electronic computers)
Department:	Electrical and Computer Engineering Electric Engineering
Advisor:	David Keezer
Degree:	Ph.D.

All materials in SMARTech are protected under U.S. Copyright Law and all rights are reserved, unless otherwise specifically indicated on or in the materials.

Files in this item

Files	Size	Format	View
newman_kimberly_e_199905_phd_493758.pdf	11.62Mb	PDF	View/ Open

This item appears in the following Collection(s)

Georgia Tech Theses and Dissertations [18339]
School of Electrical and Computer Engineering Theses and Dissertations [2404]

Show full item record