Reconfigurable equalization for 10-Gb/sec serial data links in a 0.18-μm CMOS technology
Bien, Franklin Young-Jae
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The objective of the proposed research is to realize a 10-Gb/sec serial data link over band-limited channels, such as backplanes, multi-mode fiber, and copper-based cables that were originally designed for data rates less than 1Gb/sec. This is achieved using electrical equalization implemented in an integrated circuit (IC). To successfully compensate for various band-limited channels at the targeted data rate with a single equalizer IC, a reconfigurable equalizer topology is proposed. In order to realize the proposed goal, various channels are characterized of their forward transmission frequency response. Based on the measured channel data, system simulations are performed to identify the required specifications for IC implementation. This provides information such as optimal number of taps, fractionally-spaced tap delay, and tap coefficients for the proposed IC. With the obtained system requirements, IC building blocks are designed and fabricated in a 0.18- and #956;m CMOS technology. The fully-integrated reconfigurable CMOS equalizer provides a single-chip solution for compensating various band-limited channels. This enables 10-Gb/sec serial data transmission achieving signal integrity beyond their designed specifications.