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dc.contributor.authorAggarwal, Ankuren_US
dc.date.accessioned2007-03-27T18:23:03Z
dc.date.available2007-03-27T18:23:03Z
dc.date.issued2006-11-17en_US
dc.identifier.urihttp://hdl.handle.net/1853/14096
dc.description.abstractWith the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher interconnections densities. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches. Other approaches such as compliant interconnects require lengthy connections and are limited in terms of electrical properties. A novel chip-package interconnection technology is developed to address the IC packaging requirements and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. This thesis investigates the electrical and mechanical performance of nano-structured interconnections through modeling and test vehicle fabrication. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.en_US
dc.format.extent37212163 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectFine pitchen_US
dc.subjectChipen_US
dc.subjectNano-copperen_US
dc.subjectNano-nickelen_US
dc.subjectPackageen_US
dc.subjectInterconnectionsen_US
dc.subjectNanoen_US
dc.subject.lcshNanostructured materials Electric propertiesen_US
dc.titleChip-Package Nano-Structured Copper and Nickel Interconnections with Metallic and Polymeric Bonding Interfacesen_US
dc.typeDissertationen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMaterials Science and Engineeringen_US
dc.description.advisorCommittee Chair: Tummala, Rao; Committee Member: Liu, Meilin; Committee Member: Swaminathan, Madhavan; Committee Member: Vandentop, Gilroy; Committee Member: Wong, CPen_US


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