Built-In Self Test and Calibration of RF Systems for Parametric Failures
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This thesis proposes a multifaceted production test and post-silicon yield enhancement framework for RF systems. The three main components of the proposed framework are the design, production test, and post-test phase of the overall integrated circuit (IC) development cycle. First, a circuit-sizing method is presented for incorporating test considerations into algorithms for automatic circuit synthesis/device resizing. The sizing problem is solved by using a cost metric that can be incorporated at minimal computational cost into existing optimization tools for manufacturing yield enhancement. Along with the circuit-sizing method introduced in the design phase, a low-cost test and diagnosis method is presented for multi-parametric faults in wireless systems. This test and diagnosis method allows accurate prediction of the end-to-end specifications as well as for the specifications of all the embedded modules. The procedure is based on application of optimized test stimulus and the use of a simple diode-based envelope detector to extract the transient test response envelope at RF signal nodes. This eliminates the need to make RF measurements using expensive standard testers. To further improve the parametric yield of RF circuits, a performance drift-aware adaptation scheme is proposed that automatically compensates for the loss of circuit performance in the presence of process variations. This work includes a diagnosis algorithm to identify faulty circuits within the system and a compensation process that adjusts tunable components to reduce the effects of performance variations. As a result, all the mentioned components contribute to producing a low-cost production test and to enhancing post-silicon parametric yield.