Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis
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As semiconductor technology advances into the nano-scale era and more functional blocks are added into systems on chip (SoC), the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of circuit performance degradation comes from deterministic within-die variation from lithography imperfections and Cu interconnect chemical mechanical polishing (CMP). To determine how these within-die variations impact circuit performance, a new analysis tool is required. Thus a methodology has been proposed to involve layout-dependent within-die variations in static timing analysis. The methodology combines a set of scripts and commercial tools to analyze a full chip. The tool has been applied to analyze delay of ISCAS85 benchmark circuits in the presence of imperfect lithography and CMP variation. Also, this thesis presents a methodology to generate test sets to diagnose the sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to physical mechanisms and to distinguish among different sources of within-die variation. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose lithography-caused delay faults. The effectiveness in diagnosis is evaluated for ISCAS85 benchmark circuits.