Design of High Speed Packages and Boards Using Embedded Decoupling Capacitors.
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Miniaturization of electronic products due to the current trend in the electronics industry has led to the integration of components within the chip and package. Traditionally, individual decoupling capacitors placed on the surface of the board or the package have been used to decouple active switching circuits. However, with an increase in the clock rates and its harmonics with technology nodes, decoupling has to be provided in the GHz range. Discrete decoupling capacitors are no longer effective in this region because of the increased inductive effects of the current paths of the capacitors, which limits its effectiveness in the tens of MHz range. The use of embedded individual thick film capacitors within the package is a feasible solution for decoupling core logic above 100 MHz. They overcome the limitations of SMDs (Surface Mount Discretes), primarily in decoupling active circuits in the mid-frequency band. Inclusion of embedded planar capacitors in the board stack up have shown improvements in the overall impedance profile and have shown to exhibit better noise performance. The main contributor to the superior performance is the reduced inductive effects of the power-ground planes because of the thinner dielectrics of the embedded capacitor. The modeling, measurement and characterization of embedded decoupling capacitors in the design of PDNs (Power Distribution Networks) has been investigated in this thesis.