Probabilistic CMOS (PCMOS) in the Nanoelectronics Regime

Abstract

Motivated by the necessity to consider probabilistic approaches to future designs, the main objective of this thesis was to develop and characterize energy efficient probabilistic CMOS (PCMOS) circuits that can be used to implement low energy computing platforms. The simplest circuit characterized was a PCMOS inverter (switch). An analytical model relating the energy consumption per switching (E) of this switch to its probability of correctness, p was derived. This characterization can also be used to evaluate the energy and performance savings that are achieved by PCMOS switch based computing platforms. The characterization of a PCMOS inverter was also extended to larger circuits whose probabilistic behavior was analyzed by first developing probability models of primitive gates, which were then input to a graph-based model to find the probabilities of larger circuits. The analysis of larger probabilistic circuits provides a basis for analyzing probabilistic behaviors due to noise in future technologies, and can be used in probabilistic design and synthesis methods to improve circuit reliability. Another important design criterion is the speed of a PCMOS circuit. The trade-offs between the energy, speed, and p of PCMOS circuits were also analyzed. Based on this study, various methods were proposed to optimize energy delay product (EDP) and p under given constraints on p, performance, and EDP. The sensitivity of the analysis with respect to variations in temperature, supply voltage, and threshold voltage was also considered.