Signal to power coupling and noise induced jitter in differential signaling
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Differential interconnects are extensively used in high-speed digital circuits at fast data rates and in environments of high noise like backplanes. For such applications they are preferred over single-ended lines owing to their ability to reject common-mode noise. Differential schemes like Low Voltage Differential Signaling (LVDS) are used for wireless base stations and ATM switches in telecommunication applications, flat panel displays and servers and for system-level clock distribution. LVDS applications use data rates from 100 Mbps to about 1.5 Gbps and are expected to be highly immune to noise. However, noise will also be injected into differential signals at these high data rates, if there are irregularities in the interconnect setup. These anomalies may be via transitions from differential lines through power planes in power distribution systems, via stubs, asymmetric lengths of differential lines, different transition points for each of the differential vias etc. The differential setup is expected to be immune to such imbalances; however, investigation of these discontinuities indicate that sufficient signal energy can be leaked to power distribution networks (PDN) of packages and boards. The effect of this energy loss was examined in time-domain and was found to cause signal integrity effects like jitter. Irregular differential structures were compared with the equivalent single-ended configuration and symmetrical perfect differential lines. This thesis work quantifies signal to power coupling caused by irregular differential structures in the presence of PDN planes in frequency domain. Presence of noise in differential signaling is verified through a set of test vehicles. The jitter induced as a result of signal to power coupling from differential lines was also investigated.