Estimation and optimization of layout parasitics for silicon-based millimeter-wave integrated circuits
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Millimeter-wave has been a medium for automotive, sensor, and defense applications for a long time. But, a fully integrated silicon-based transceiver at 60 GHz or higher frequencies has become the driving force for recent research activities in integrated millimeter-wave (MMW) circuit designs. However, no integrated compact high-performance millimeter-wave system can be designed without accurate estimation and optimization of layout parasitics. In this dissertation, the estimation, modeling and optimization of parasitic effects as well as the verification of extraction methodologies for RF/MMW applications are investigated. Different circuit design- and layout-examples are considered with stress on the inclusion and optimization of wire/interconnect parasitics. A novel methodology is proposed to reduce the number of design-passes and to include layout parasitics in the design optimization procedure. An automated verification procedure for existing parasitic extraction tools is developed. Neural-network-based models are used to demonstrate the effectiveness of artificial intelligence techniques for characterizing parasitic components. The parasitic sensitivities for selected millimeter-wave circuits are demonstrated, and a parasitic benchmarking procedure is developed using MMW oscillators. Measurement results of several circuits that are implemented in state-of-the-art CMOS and SiGe-BiCMOS processes are used to demonstrate the role of parasitics and the systematic design methodology including parasitics.