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dc.contributor.authorSen, Padmanavaen_US
dc.date.accessioned2009-01-22T15:48:02Z
dc.date.available2009-01-22T15:48:02Z
dc.date.issued2007-11-06en_US
dc.identifier.urihttp://hdl.handle.net/1853/26585
dc.description.abstractMillimeter-wave has been a medium for automotive, sensor, and defense applications for a long time. But, a fully integrated silicon-based transceiver at 60 GHz or higher frequencies has become the driving force for recent research activities in integrated millimeter-wave (MMW) circuit designs. However, no integrated compact high-performance millimeter-wave system can be designed without accurate estimation and optimization of layout parasitics. In this dissertation, the estimation, modeling and optimization of parasitic effects as well as the verification of extraction methodologies for RF/MMW applications are investigated. Different circuit design- and layout-examples are considered with stress on the inclusion and optimization of wire/interconnect parasitics. A novel methodology is proposed to reduce the number of design-passes and to include layout parasitics in the design optimization procedure. An automated verification procedure for existing parasitic extraction tools is developed. Neural-network-based models are used to demonstrate the effectiveness of artificial intelligence techniques for characterizing parasitic components. The parasitic sensitivities for selected millimeter-wave circuits are demonstrated, and a parasitic benchmarking procedure is developed using MMW oscillators. Measurement results of several circuits that are implemented in state-of-the-art CMOS and SiGe-BiCMOS processes are used to demonstrate the role of parasitics and the systematic design methodology including parasitics.en_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectLayout optimizationen_US
dc.subjectCMOSen_US
dc.subject60GHz systemsen_US
dc.subjectMillimeter-wave design centeringen_US
dc.subjectParasitic modelingen_US
dc.subjectSiGeen_US
dc.subject.lcshMillimeter waves
dc.subject.lcshSemiconductors
dc.subject.lcshAlgorithms
dc.titleEstimation and optimization of layout parasitics for silicon-based millimeter-wave integrated circuitsen_US
dc.typeDissertationen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.advisorCommittee Chair: Dr. Joy Laskar; Committee Member: Dr. Chang- Ho Lee; Committee Member: Dr. Federico Bonetto; Committee Member: Dr. John D. Cressler; Committee Member: Dr. John Papapolymerou; Committee Member: Dr. Linda S. Miloren_US


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