Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design
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A method to implement high-speed pulse shaping filters has been discussed. This technique uses a unique look up table based architecture implemented in 90nm CMOS using a standard cell based ASIC flow. This method enables the implementation of pulse shaping filters for multi-giga bit per second data transmission. In this work a raised cosine FIR filter operating at 4 GHz has been designed. Various Implementation issues and solutions encountered during the synthesis and layout stages have been discussed. In the second portion of this work, the design of a unique address based serial peripheral interface (SPI) for initializing, calibrating and controlling various blocks in a large system has been discussed. Some modifications have been made to the standard four-wire SPI protocol to enable high control speeds with lesser number of top-level pads. This interface has been designed to function in the duplex mode to do both read and write operations.