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dc.contributor.authorWoo, Dong Hyuk
dc.contributor.authorFryman, Joshua B.
dc.contributor.authorKnies, Allan D.
dc.contributor.authorLee, Hsien-Hsin Sean
dc.date.accessioned2009-03-05T22:16:28Z
dc.date.available2009-03-05T22:16:28Z
dc.date.issued2008
dc.identifier.urihttp://hdl.handle.net/1853/27232
dc.description.abstractHeterogeneous multi-core processors have emerged as an energy- and area-efficient architectural solution to improving performance for domain-specific applications such as those with a plethora of data-level parallelism. These processors typically contain a large number of small, compute-centric cores for acceleration while keeping one or two high-performance ILP cores on the die to guarantee single-thread performance. Although a major portion of the transistors are occupied by the acceleration cores, these resources will sit idle when running unparallelized legacy codes or the sequential parts of an application. To address this under-utilization issue, in this paper, we introduce Chameleon, a flexible heterogeneous multi-core architecture to virtualize these resources for enhancing memory performance when running sequential programs. The Chameleon architecture can dynamically virtualize the idle acceleration cores into a last-level cache, a data prefetcher, or a hybrid between these two techniques. In addition, Chameleon can operate in an adaptive mode which dynamically configures the acceleration cores between the hybrid mode and the prefetch-only mode by monitoring the effectiveness of Chameleon caching scheme. In our evaluation using SPEC2006 benchmark suite, different levels of performance improvements were achieved in different modes for different applications. In the case of the adaptive mode, Chameleon improves the performance of SPECint06 and SPECfp06 by 33% and 22% on average. When considering only memory-intensive applications, Chameleon improves the system performance by 53% and 33%.en
dc.language.isoen_USen
dc.publisherGeorgia Institute of Technologyen
dc.relation.ispartofseriesCERCS ; GIT-CERCS-08-11en
dc.subjectCache designen
dc.subjectCachingen
dc.subjectComputer architectureen
dc.subjectCoresen
dc.subjectLatencyen
dc.subjectMulti-core processoren
dc.subjectPrefetcheren
dc.subjectProgrammingen
dc.titleChameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetchingen
dc.typeTechnical Reporten
dc.contributor.corporatenameGeorgia Institute of Technology. School of Electrical and Computer Engineering
dc.contributor.corporatenameIntel Corporation. Microprocessor Technology Labs
dc.contributor.corporatenameIntel Research Berkeley


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