Show simple item record

dc.contributor.authorLee, Sangilen_US
dc.date.accessioned2009-08-26T18:16:39Z
dc.date.available2009-08-26T18:16:39Z
dc.date.issued2009-07-06en_US
dc.identifier.urihttp://hdl.handle.net/1853/29755
dc.description.abstractFlip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer pitch area array interconnects structured FCIP can be achieved using no-flow underfill assembly process. Using the assembly process, a high, stable yield assembly process recently reported with eutectic lead-tin solder interconnections, 150 µm pitch, and I/O counts in excess of 3000. The assembly process reported created a large number of voids among solder interconnects in FCIP. The voids formed among solder interconnections can propagate, grow, and produce defects such as solder joint cracking and solder bridging. Moreover, these voids can severely reduce reliability performance. Indeed, many studies were conducted to examine the void formation in FCIP. Based on the studies, flip chip geometric design, process conditions, and material formulation have been considered as the potential causes of void formation. However, the present research won't be able to identify the mechanism of void formation, causing a lot of voids in assembly process without consideration of chemical reaction in the assembly process with a fine-pitch, high I/O density FCIP. Therefore, this research will present process technology necessary to achieve high yields in FCIP assemblies using no-flow underfills and investigate the underlying problem of underfill void formation in these assemblies. The plausible causes of void formation will be investigated using experimental techniques. The techniques will identify the primary source of the void formation. Besides, theoretical models will be established to predict the number of voids and to explain the growth behavior of voids in the FCIP. The established theoretical models will be verified by experiments. These models will validate with respect to the relationship between process parameters to achieve a high yield and to minimize voids in FCIP assemblies using no-flow underfill materials regarding process as well as material stand points. Eventually, this research provides design guideline achieving a high, stable yield and void-free assembly process.en_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectNanoen_US
dc.subjectNucleationen_US
dc.subjectVoiden_US
dc.subjectNo-flowen_US
dc.subjectFlip chipen_US
dc.subject.lcshFlip chip technology
dc.subject.lcshMicroelectronic packaging
dc.subject.lcshSolder and soldering
dc.titleFundamental study of underfill void formation in flip chip assemblyen_US
dc.typeDissertationen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMechanical Engineeringen_US
dc.description.advisorCommittee Chair: Baldwin, Daniel; Committee Member: Colton, Jonathan; Committee Member: Ghiaasiaan, Mostafa; Committee Member: Moon, Jack; Committee Member: Tummala, Raoen_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record