Power- and area-efficient single SISO architecture of Turbo decoder
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In this paper, we propose a power- and area-efficient architecture of Turbo decoder. In order to improve the nonfunctional performance metrics such as power consumption and area, we use the trade-off method between bit error rate (BER) performance and the two non-functional performance metrics. Our proposed architecture shows about 16.7% reduction in power consumption and about 22.5% reduction in area compared to the general architecture.
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