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dc.contributor.authorBhatele, Abhinav S.en_US
dc.date.accessioned2010-04-27T19:53:45Z
dc.date.available2010-04-27T19:53:45Z
dc.date.issued2010-03-30
dc.identifier.urihttp://hdl.handle.net/1853/32764
dc.descriptionAbhinav Bhatele, Ph.D. student at the Parallel Programming Lab at the University of Illinois presented a lecture on March 30, 2010 at 2:00 pm in room 1116 E of the Klaus Advanced Computing Building on the Georgia Tech campusen_US
dc.descriptionRuntime: 57:31 minutesen_US
dc.description.abstractParallel computing is entering the era of petascale machines. This era brings enormous computing power to us and new challenges to harness this power efficiently. Machines with hundreds of thousands of processors already exist, connected by complex interconnect topologies. Network contention is becoming an increasingly important factor affecting overall performance. The farther different messages travel on the network, greater is the chance of resource sharing between messages and hence, of contention. Recent studies on IBM Blue Gene and Cray XT machines have shown that under contention, message latencies can be severely affected. Mapping of communicating tasks on nearby processors can minimize contention and lead to better application performance. In this talk, I will propose algorithms and techniques for automatic mapping of parallel applications to relieve the application developers of this burden. I will first demonstrate the effect of contention on message latencies and use these studies to guide the design of mapping algorithms. I will introduce the hop-bytes metric for the evaluation of mapping algorithms and suggest that it is a better metric than the previously used maximum dilation metric. I will then discuss in some detail, the mapping framework which comprises of topology aware mapping algorithms for parallel applications with regular and irregular communication patterns.en_US
dc.format.extent57:31 minutes
dc.language.isoen_USen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.relation.ispartofseriesComputational Science and Engineering Seminar Seriesen_US
dc.subjectMappingen_US
dc.subjectAlgorithmsen_US
dc.subjectSupercomputersen_US
dc.subjectTopologyen_US
dc.titleAutomating Topology Aware Task Mapping on Large Supercomputersen_US
dc.typeLectureen_US
dc.typeVideoen_US
dc.contributor.corporatenameUniversity of Illinois at Urbana-Champaign. Parallel Programming Laboratoryen_US


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