Operation of inverse mode SiGe HBTs and ultra-scaled CMOS devices in extreme environments
MetadataShow full item record
The objective of this work is to investigate the performance of SiGe HBTs and scaled CMOS devices in extreme environments. In this work, the inverse mode operation of SiGe HBTs is investigated as a potential solution to the vulnerability of SiGe HBTs to single event effects. The performance limitations of SiGe HBTs operating in inverse mode are investigated through an examination of the effects of scaling on inverse mode performance and optimization schemes for inverse mode performance enhancements are discussed and demonstrated. In addition the performance of scaled MOSFETs, that constitute the digital backbone of any BiCMOS technology, is investigated under radiation exposure and cryogenic temperatures. Extreme environments and their effects on semiconductor devices are introduced in Chapter 1. The immunity of 90nm MOSFETs to total ionizing dose damage under proton radiation is demonstrated. Inverse mode operation of SiGe HBTs is introduced in Chapter 2 as a potential radiation hard solution by design. The effect of scaling on inverse mode performance of SiGe HBTs is investigated and the performance limitations in inverse mode are identified. Optimization schemes for improving inverse mode performance of SiGe HBTs are discussed in Chapter 3. Inverse mode performance enhancement is demonstrated experimentally in optimized device structures manufactured in a commercial third generation SiGe HBT BiCMOS platform. Further, a cascode device structure, the combines the radiation immunity of an inverse mode structure with the performance of a forward mode common emitter device is XIV discussed. Finally, idealized doping profiles for inverse mode performance enhancement is discussed through TCAD simulations. The cryogenic performance of inverse mode SiGe HBTs are discussed in Chapter 4. A novel base current behavior at cryogenic temperature is identified and its effect on the inverse mode performance is discussed. Matching performance of a 90nm bulk CMOS technology at cryogenic temperatures is investigated experimentally and through TCAD simulations in Chapter 5. The effect of various process parameters on the temperature sensitivity of threshold voltage mismatch is discussed. The potential increase of mismatch in subthreshold MOSFETs operating in cryogenic temperatures due to hot carrier effects is also investigated.