Digital communication and control circuits for 60ghz fully integrated CMOS digital radio

Abstract

Emerging "bandwidth hungry" applications such as high definition video distribution and ultra fast multimedia side-loading have extended the need for multi-gigabit wireless solutions beyond the reach of conventional WLAN technology or even more recently emerging UWB and MIMO systems. The availability of 7GHz of unlicensed bandwidth in the 60GHz spectrum, represents a unique opportunity to address such data-throughput requirements. The 60GHz Integrated CMOS digital radio chipset comprises of PHY and MAC layers, RF transceiver, High-Speed Digital Interface and an underlying Serial Communication Fabric. To have a complete communication solution compliant with the latest ECMA-369, ISO/DIS 13156 and IEEE 802.15.3c standards, we build a million gate digital implementation of MAC and PHY. The Serial Peripheral Interface (SPI) serves as the bridge between the higher layers in the communication stack (PAL-MAC) and the lower layers like PHY-RF Front End. The MAC module can setup the communication link on the fly by tuning parameters such as operating channel, channel bonding and bandwidth, data rates, error correction mechanisms, handshaking mechanisms, etc, by using the SPI to communicate with internal components. The SPI interface plays a crucial rule in not only this, but also during the testing and debug phase. Operation of each of the RF modules is monitored through the serial interface using local SPI slaves which are hooked up to the 4-wire serial bus running all through the chip. The SPI host controller emulates an embedded protocol analyzer. For calibration and fine tuning purposes, digital settings can also be loaded onto these modules through the SPI interface. R-2R DACs are used to convert these commands into analog voltages which then provide a tunable bias to the RF and mixed-signal modules. Other key functions of this serial communication and control interface are: Initialization of all of the RF and mixed signal modules, DC calibration of data converter, PLL and other mixed-signal modules, data acquisition, parametric tuning for digital modules such as linear equalizer, Gain Control loops (AGC, VGA), etc. Ultra high speed digital Input-Output buffers are used to provide an external data interface to the radio chipset. These high speed I/Os are also used in the gbps (gigabit-per-second) link for data transfer between the RF transceiver chip and the PHY-MAC baseband chip. The IOs are expected to comply with different signaling standards such as LVDS, SLVS200, SLVS400, etc. A robust system involves a meticulous pad ring design with proper power domains and power cuts. Full-chip integration of the digital PHY, MAC, peripheral logic and IO ring is done in a semi-custom fashion.