Large signal model development and high efficiency power amplifier design in cmos technology for millimeter-wave applications
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This dissertation presents a novel large signal modeling approach which can be used to accurately model CMOS transistors used in millimeter-wave CMOS power amplifiers. The large signal model presented in this work is classified as an empirical compact device model which incorporates temperature-dependency and device periphery scaling. These added features allow for efficient design of multi-stage CMOS power amplifiers by virtue of the process-scalability. Prior to the presentation of the details of the model development, background is given regarding the 90nm CMOS process, device test structures, de-embedding methods and device measurements, all of which are necessary preliminary steps for any device modeling methodology. Following discussion of model development, the design of multi-stage 60GHz Class AB CMOS power amplifiers using the developed model is shown, providing further model validation. The body of research concludes with an investigation into designing a CMOS power amplifier operating at frequencies close to the millimeter-wave range with a potentially higher-efficiency class of power amplifier operation. Specifically, a 24GHz 130nm CMOS Inverse Class F power amplifier is simulated using a modified version of the device model, fabricated and compared with simulations. This further demonstrates the robustness of this device modeling method.