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    Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication

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    COPE_229.pdf (2.049Mb)
    Date
    2005-08
    Author
    Mule’, Anthony V.
    Villalaz, Ricardo A.
    Joseph, Paul Jayachandran
    Naeemi, Azad
    Kohl, Paul A.
    Gaylord, Thomas K.
    Meindl, James D.
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    Abstract
    Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.
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    http://hdl.handle.net/1853/46949
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