| dc.contributor.author | Patel, Girish N. | en_US |
| dc.contributor.author | Reid, Michael S. | en_US |
| dc.contributor.author | Schimmel, David E. | en_US |
| dc.contributor.author | DeWeerth, Stephen P. | en_US |
| dc.date.accessioned | 2013-06-12T20:22:57Z | |
| dc.date.available | 2013-06-12T20:22:57Z | |
| dc.date.issued | 2006-02 | |
| dc.identifier.citation | Patel G.N., Reid M.S., Schimmel D.E., DeWeerth S.P., “An asynchronous architecture for modeling intersegmental neural communication,” IEEE Transactions on VLSI Systems, 14, 2, 97-110 (February 2006) | en_US |
| dc.identifier.issn | 1063-8210 | |
| dc.identifier.uri | http://hdl.handle.net/1853/47403 | |
| dc.description | © 2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works | en_US |
| dc.description | DOI: 10.1109/TVLSI.2005.863762 | en_US |
| dc.description.abstract | This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented; data from this system are presented. | en_US |
| dc.language.iso | en_US | en_US |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.subject | Address event representation | en_US |
| dc.subject | AER | en_US |
| dc.subject | Asynchronous | en_US |
| dc.subject | Circuits | en_US |
| dc.subject | Central pattern generator (CPG) | en_US |
| dc.subject | Neurobiological | en_US |
| dc.subject | Modeling | en_US |
| dc.subject | Neuromorphic engineering | en_US |
| dc.subject | Silicon neuron | en_US |
| dc.subject | VLSI architecture | en_US |
| dc.title | An asynchronous architecture for modeling intersegmental neural communication | en_US |
| dc.type | Article | en_US |
| dc.contributor.corporatename | Georgia Institute of Technology | en_US |
| dc.publisher.original | Institute of Electrical and Electronics Engineers | en_US |
| dc.identifier.doi | 10.1109/TVLSI.2005.863762 | |
