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dc.contributor.authorPatel, Girish N.en_US
dc.contributor.authorReid, Michael S.en_US
dc.contributor.authorSchimmel, David E.en_US
dc.contributor.authorDeWeerth, Stephen P.en_US
dc.date.accessioned2013-06-12T20:22:57Z
dc.date.available2013-06-12T20:22:57Z
dc.date.issued2006-02
dc.identifier.citationPatel G.N., Reid M.S., Schimmel D.E., DeWeerth S.P., “An asynchronous architecture for modeling intersegmental neural communication,” IEEE Transactions on VLSI Systems, 14, 2, 97-110 (February 2006)en_US
dc.identifier.issn1063-8210
dc.identifier.urihttp://hdl.handle.net/1853/47403
dc.description© 2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksen_US
dc.descriptionDOI: 10.1109/TVLSI.2005.863762en_US
dc.description.abstractThis paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented; data from this system are presented.en_US
dc.language.isoen_USen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectAddress event representationen_US
dc.subjectAERen_US
dc.subjectAsynchronousen_US
dc.subjectCircuitsen_US
dc.subjectCentral pattern generator (CPG)en_US
dc.subjectNeurobiologicalen_US
dc.subjectModelingen_US
dc.subjectNeuromorphic engineeringen_US
dc.subjectSilicon neuronen_US
dc.subjectVLSI architectureen_US
dc.titleAn asynchronous architecture for modeling intersegmental neural communicationen_US
dc.typeArticleen_US
dc.contributor.corporatenameGeorgia Institute of Technologyen_US
dc.publisher.originalInstitute of Electrical and Electronics Engineersen_US
dc.identifier.doi10.1109/TVLSI.2005.863762


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