A Broadband Passive Delay Line Structure in 0.18 Micron CMOS For A Gigabit Feed Forward Equalizer
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This project focusses on the design of a high speed passive delay line for use in a Feed Forward Equalizer (FFE). The FFE is used to equalize a 20 Gbp/s throughput PAM-4 signal after transmission through a 20-inch FR4 backplane channel. Inductor electromagnetic simulations are used to design an inductor for use in the passive delay line and a lumped element inductor model is presented. Measurement results show performance of the delay line at 10 GSym/s.