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dc.contributor.authorXuan, Xiangdongen_US
dc.date.accessioned2005-03-01T19:20:32Z
dc.date.available2005-03-01T19:20:32Z
dc.date.issued2004-08-04en_US
dc.identifier.urihttp://hdl.handle.net/1853/4776
dc.description.abstractFacing the constantly increasing reliability challenges under technology scaling, the topics in IC reliability technique have been receiving serious attention during recent years. In this work, based on the understanding of existing physical failure models that have been concentrating on the pre-fab circuits, a set of revised models for major failure mechanisms such as electromigration, hot-carrier, and gate oxide wear-out are created. Besides the modeling of degradation behaviors for circuits in design phase, these models tend to deal with the post-fab device characteristics with the presence of physical defects. In addition, the simulation work has been taken from device level to circuit level hierarchically, presenting the evaluation of circuit level reliability such as degradations of circuit level specs and circuit lifetime prediction. For post-fab ICs under electromigration, the expected circuit lifetime is calculated based on statistical processes and the probability theory. By incorporating all physics-of-failure models and applying circuit level simulation approaches, an IC reliability simulator called ARET (ASIC reliability evaluation tool) has been developed. Besides the reliability evaluation, the reliability hotspot identification function is developed in ARET, which is a key step for conducting IC local design-for-reliability approaches. ARET has been calibrated with a series of stress tests conducted at The Boeing Company. Design-for-reliability (DFR) is a very immature technical area, which has been becoming critical with the continuously shrinking reliability safety margin. A novel concept, local design-for-reliability is proposed in this work. This DFR technique is closely based on reliability simulation and hotspot identification. By redesigning the circuit locally around reliability hotspots, this DFR approach offers the overall reliability improvement with the maintained circuit performance. Various DFR algorithms are developed for different circuit situations. The experiments on designed and benchmark circuits have shown that significant circuit reliability improvements can be obtained without compromising performance by applying these DFR algorithms.en_US
dc.format.extent1474683 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectReliability simulationen_US
dc.subjectDesign-for-reliability
dc.subjectIC reliability
dc.subject.lcshMetal oxide semiconductors, Complementary Reliability Computer simulationen_US
dc.subject.lcshIntegrated circuits Reliability Computer simulationen_US
dc.titleAnalysis and design of reliable mixed-signal CMOS circuitsen_US
dc.typeDissertationen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.advisorCommittee Chair: Chatterjee, Abhijit; Committee Member: Keezer, David; Committee Member: May, Gary; Committee Member: Singh, Adit; Committee Member: Swaminathan, Madhavanen_US


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