Proximity Lithography in Sub-10 Micron Circuitry for Packaging Substrate

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Date
2010-11Author
Wang, Fengtao
Liu, Fuhan
Kong, Linghua
Sundaram, Venky
Tummala, Rao R.
Adibi, Ali
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Show full item recordAbstract
Rapid changes in the semiconductor industry
will continue toward higher functionality that leads to higher
input/outputs (I/O) counts, pushing packaging towards higher
density architectures. In the next two to three years, the I/O pitch
will fall within 100 μm for area array die and 30 μm for periphery
die. That raises an important question to the packaging industry:
How will the rapid shrinkage of the I/O pitch affect the package
substrate for chip attaching? The answer is sub-10 micron copper
line technology. Theoretical and experimental studies on the
limitations of using mercury i-line ultraviolet photolithography
have been carried at the Packaging Research Center at Georgia
Tech. Furthermore, ultra fine copper line routing substrates
are demonstrated for flip chip attaching by using semi-additive
metallization process.
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