Modeling of Simultaneous Switching Noise in On-Chip and Package Power Distribution Networks Using Conformal Mapping, Finite Difference Time Domain and Cavity Resonator Methods
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This thesis focused on modeling and simulation of simultaneous switching noise in packages as well as integrated circuits and the focus was mainly on the latter. Efficient and accurate methods have been developed for modeling the coupling due to SSN in multi-layered planes arising in electronic packages, extraction of the power grid in integrated circuits and simulation of the power supply noise in large size networks arising in power distribution network. These methods include conformal mapping, finite difference time domain and cavity resonator methods, using which the electrical performance of the power distribution system in a high speed electronic product can be predicted. The model developed for field penetration captured the effect of the magnetic field penetrating through planes in multi-layered packages. Analytical model for the extraction of the interconnect parasitics for a regular on-chip power grid has been presented. Complex image technique has been applied for modeling the dispersive interconnect on lossy silicon substrate. The Debye rational approximation has been used to approximate the RLGC parameters in order to simulate the frequency dependent elements in the time domain. The simulation of the entire network of the full-chip power grid has been carried out using the modified FDTD expressions. Several aspects of characterizing the generic on-chip power distribution network have been presented. The crossover capacitance has been evaluated using analytical model derived from conformal mapping. An analytical model has been proposed to extract parameters of on-chip multi-conductor transmission lines, which guarantees the stability and is applicable to general distribution of multi-conductor transmission lines. The above modeling procedures have been incorporated into a computer program, which generates the power grid model from the layout of chip power distribution networks automatically. Research on 3-D on-chip power distribution networks has been presented. The complex image technique has been extended from microstrip-type interconnects to stripline-type interconnects. Macromodel images have been derived with closed form expressions to capture the loss mechanism of the multiple conductive substrates. The effect of 3-D integration on switching noise has been illustrated in the time domain using examples.