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    Oscillation Control in CMOS Phase-Locked Loops

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    terlemez_bortecene_200412_phd.pdf (7.039Mb)
    Date
    2004-11-22
    Author
    Terlemez, Bortecene
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    Abstract
    Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.
    URI
    http://hdl.handle.net/1853/4841
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    • Georgia Tech Theses and Dissertations [23403]
    • School of Electrical and Computer Engineering Theses and Dissertations [3303]

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