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dc.contributor.authorShell, Michael Daviden_US
dc.date.accessioned2005-03-01T19:39:30Z
dc.date.available2005-03-01T19:39:30Z
dc.date.issued2004-12-01en_US
dc.identifier.urihttp://hdl.handle.net/1853/4892
dc.description.abstractThis work develops an exact logical operation model to predict the performance of the all-optical shared-memory architecture (OSMA) class of packet switches and provides a means to obtain a reasonable approximation of OSMA switch performance within certain types of networks, including the Banyan family. All-optical packet switches have the potential to far exceed the bandwidth capability of their current electronic counterparts. However, all-optical switching technology is currently not mature. Consequently, all-optical switch fabrics and buffers are more constrained in size and can cost several orders of magnitude more than those of electronic switches. The use of shared-memory buffers and/or links with multiple parallel channels (channel grouping) have been suggested as ways to maximize switch performance with buffers of limited size. However, analysis of shared-memory switches is far more difficult than for other commonly used buffering strategies. Obtaining packet loss performance by simulation is often not a viable alternative to modeling if low loss rates or large networks are encountered. Published models of electronic shared-memory packet switches (ESMP) have primarily involved approximate models to allow analysis of switches with a large number of ports and/or buffer cells. Because most ESMP models become inaccurate for small switches, and OSMA switches, unlike ESMP switches, do not buffer packets unless contention occurs, existing ESMP models cannot be applied to OSMA switches. Previous models of OSMA switches were confined to isolated (non-networked), symmetric OSMA switches using channel grouping under random traffic. This work is far more general in that it also encompasses OSMA switches that (1) are subjected to bursty traffic and/or with input links that have arbitrary occupancy probability distributions, (2) are interconnected to form a network and (3) are asymmetric.en_US
dc.format.extent2158500 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectPacket switchingen_US
dc.subjectOptical buffering
dc.subjectNetworks
dc.subjectMarkov models
dc.subjectChannel grouping
dc.subjectBursty traffic
dc.subjectBanyan networks
dc.subjectAsymmetric
dc.subjectAnalytical modeling
dc.subjectAll-optical networks
dc.subjectShared-memory switches
dc.subject.lcshOptical data processingen_US
dc.subject.lcshPacket switching (Data transmission) Mathematical modelsen_US
dc.subject.lcshComputer networksen_US
dc.subject.lcshMarkov processesen_US
dc.subject.lcshOptical communicationsen_US
dc.titleCascaded All-Optical Shared-Memory Architecture Packet Switches Using Channel Grouping Under Bursty Trafficen_US
dc.typeDissertationen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.advisorCommittee Chair: Joseph L. A. Hughes; Committee Member: Henry L. Owen; Committee Member: John A. Copeland; Committee Member: Richard M. Fujimoto; Committee Member: W. Russell Callenen_US


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