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dc.contributor.advisorPrvulovic, Milos
dc.contributor.advisorZajic, Alenka
dc.contributor.authorOh, Jungju
dc.date.accessioned2014-01-13T16:19:18Z
dc.date.available2014-01-13T16:19:18Z
dc.date.created2013-12
dc.date.issued2013-08-05
dc.date.submittedDecember 2013
dc.identifier.urihttp://hdl.handle.net/1853/50219
dc.description.abstractIn recent years, the number of available cores in a processor are increasing rapidly while the pace of performance improvement of an individual core has been lagged. It led application developers to extract more parallelism from a number of cores to make their applications run faster. However, writing a parallel program that scales well with the increasing core counts is challenging. Consequently, many parallel applications suffer from performance bugs caused by scalability limiters. We expect core counts to continue to increase for the foreseeable future and hence, addressing scalability limiters is important for better performance on future hardware. With this thesis, I propose both software frameworks and hardware improvements that I developed to address three important scalability limiters: load imbalance, barrier latency and increasing on-chip packet latency. First, I introduce a debugging framework for load imbalance called LIME. The LIME framework uses profiling, statistical analysis and control flow graph analysis to automatically determine the nature of load imbalance problems and pinpoint the code where the problems are introduced. Second, I address scalability problem of the barrier, which has become costly and difficult to achieve scalable performance. To address this problem, I propose a transmission line (TL) based hardware barrier support, called TLSync, that is orders of magnitude faster than software barrier implementation while supports many (tens) of barriers simultaneously using a single chip-spanning network. Third and lastly, I focus on the increasing packet latency in on-chip network, and propose a hybrid interconnection where a low-latency TL based interconnect is synergistically used with a high-throughput switched interconnect. Also, a new adaptive packet steering policy is created to judiciously use the limited throughput available on the low-latency TL interconnect.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subjectMany-core
dc.subjectPerformance debugging
dc.subjectLoad imbalance
dc.subjectHardware barrier
dc.subjectTransmission line
dc.subjectHybrid interconnection
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshMultiprocessors
dc.subject.lcshMemory management (Computer science)
dc.titleEfficient hardware and software assist for many-core performance
dc.typeDissertation
dc.description.degreePh.D.
dc.contributor.departmentComputer Science
thesis.degree.levelDoctoral
dc.contributor.committeeMemberConte, Tom
dc.contributor.committeeMemberKim, Hyesoon
dc.contributor.committeeMemberQureshi, Moinuddin
dc.date.updated2014-01-13T16:19:18Z


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