Experimental and theoretical assessment of Through-Silicon Vias for 3D integrated microelectronic packages
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With continued push toward 3D integrated packaging, Through-Silicon Vias (TSVs) play an increasingly important role in interconnecting stacked silicon dies. Although progress is being made in the fabrication of TSVs, experimental and theoretical assessment of their thermomechanical reliability is still in infancy. This work explores the thermomechanical reliability of TSVs through numerical models and innovative experimental characterization techniques. Starting with free-standing wafers, this work examines failure mechanisms such as Si and SiO₂ cohesive cracking as well as SiO₂/Cu interfacial cracking. Such cohesive crack propagation and interfacial crack propagation are studied using fracture mechanics finite-element modeling, and the energy available for crack propagation is determined through crack extension using the proposed centered finite-difference approach (CFDA). In parallel to the simulations, silicon wafers with TSVs are designed and fabricated and subjected to thermal shock test. Cross-sectional SEM failure analysis is carried out to study cohesive and interfacial crack initiation and propagation under thermal excursions. In addition, local micro-strain fields under thermal excursions are mapped through synchrotron X-ray diffraction. To understand the 3D to 2D strain measurement data projection process, a new data interpretation method based on beam intensity averaging is proposed and validated with measurements. Building upon the work on free-standing wafers, this research studies the package assembly issues and failure mechanisms in multi-die stacks. Comprehensive design-of-simulations study is carried out to assess the effect of various material and geometry parameters on the reliability of 3D microelectronic packages. Through experimentally-measured strain fields, thermal cycling tests, and simulations, design guidelines are developed to enhance the thermomechanical reliability of TSVs used in future 3D microelectronic packages.