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dc.contributor.advisorSwaminathan, Madhavan
dc.contributor.authorNatu, Nitish Umesh
dc.date.accessioned2014-05-22T15:23:59Z
dc.date.available2014-05-22T15:23:59Z
dc.date.created2014-05
dc.date.issued2014-02-21
dc.date.submittedMay 2014
dc.identifier.urihttp://hdl.handle.net/1853/51812
dc.description.abstractClock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subject3D IC
dc.subjectThrough silicon via
dc.subjectClock distribution network (CDN)
dc.subjectSkew
dc.subjectPropagation delay
dc.subjectAdaptive voltage
dc.subjectControllable delay
dc.subjectFPGA
dc.subjectTest vehicle
dc.subjectASIC buffer design
dc.subject.lcshThree-dimensional integrated circuits
dc.subject.lcshIntegrated circuits
dc.titleDesign and prototyping of temperature resilient clock distribution networks
dc.typeThesis
dc.description.degreeM.S.
dc.contributor.departmentElectrical and Computer Engineering
thesis.degree.levelMasters
dc.contributor.committeeMemberKeezer, David
dc.contributor.committeeMemberChatterjee, Abhijit
dc.date.updated2014-05-22T15:24:00Z


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