Design methodologies for robust low-power digital systems under static and dynamic variations
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Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The safety margin makes it difficult to meet the target performance within a limited power budget. This research explores methodologies to minimize the safety margin, thereby improving the energy efficiency of a system. The safety margin can be reduced by either minimizing the variation or adapting to the variation. This research explores three different methods to compensate for variations efficiently. First, post-silicon tuning methods for minimizing variations in 3D ICs are presented. Design methodologies to apply adaptive voltage scaling and adaptive body biasing to 3D ICs and the associated circuit techniques are explored. Second, non-design-intrusive circuit techniques are proposed for adaptation to dynamic variations. This work includes adaptive clock modulation and bias-voltage generation techniques. Third, design-intrusive methods to eliminate the safety margin are proposed. The proposed methodologies can prevent timing-errors in advance with a minimized performance penalty. As a result, the methods presented in this thesis minimize static variations and adapt to dynamic variations, thereby, enabling robust low-power operation of digital systems.