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dc.contributor.advisorNaeemi, Azad
dc.contributor.authorCeyhan, Ahmet
dc.date.accessioned2015-01-12T20:52:41Z
dc.date.available2015-01-12T20:52:41Z
dc.date.created2014-12
dc.date.issued2014-11-17
dc.date.submittedDecember 2014
dc.identifier.urihttp://hdl.handle.net/1853/53080
dc.description.abstractThe limitations of the conventional Cu/low-k interconnect technology for use in future ultra-scaled integrated circuits down to 7 nm in the year 2020 are investigated from the power/performance point of view. Compact models are used to demonstrate the impacts of various interconnect process parameters, for instance, the interconnect barrier/liner bilayer thickness and aspect ratio, on the design and optimization of a multilevel interconnect network. A framework to perform a sensitivity analysis for the circuit behavior to interconnect process parameters is created for future FinFET CMOS technology nodes. Multiple predictive cell libraries down to the 7‒nm technology node are constructed to enable early investigation of the electronic chip performance using commercial electronic design automation (EDA) tools with real chip information. Findings indicated new opportunities that arise for emerging novel interconnect technologies from the materials and process perspectives. These opportunities are evaluated based on potential benefits that are quantified with rigorous circuit-level simulations and requirements for key parameters are underlined. The impacts of various emerging interconnect technologies on the performances of emerging devices are analyzed to quantify the realistic circuit- and system-level benefits that these new switches can offer.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subjectInterconnects
dc.subjectCu/low-k
dc.subjectCarbon nanotubes
dc.subjectBenchmarking
dc.subjectTunneling FETs
dc.subjectCarbon nanotube FETs
dc.subjectPhysical design and optimization
dc.titleInterconnects for future technology generations - conventional CMOS with copper/low-k and beyond
dc.typeDissertation
dc.description.degreePh.D.
dc.contributor.departmentElectrical and Computer Engineering
thesis.degree.levelDoctoral
dc.contributor.committeeMemberDavis, Jeffrey
dc.contributor.committeeMemberMukhopadhyay, Saibal
dc.contributor.committeeMemberBakir, Muhannad
dc.contributor.committeeMemberJoshi, Yogendra
dc.date.updated2015-01-12T20:52:41Z


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