Design methodology for low power 3D-integrated image sensing system for network based applications
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This dissertation investigates a methodology that can be used to design and optimize an energy efficient 3D-integrated image sensing and compression system for network based applications. A system level model that evaluates the effect of design choices and external environmental factors to the power/performance of the system is presented. Three design principles are considered in formulating the system model. First, a multi-segment/multi-core image compression approach is presented as a combined solution with 3D-stacking to reduce the workload of the compression module, effectively increasing power efficiency of the system. Second, vertical stacking reduces the rate of heat removal from the compression module and ADC resulting in higher temperature and noise in the photodiode tier. Therefore, due to the die-to-die thermal coupling, image quality is strongly influenced by image throughput, architectural, and external environment factors. Third, heterogeneous integration of the photosensor module and compression engine is presented as a method to increase power efficiency of the system. Scaling the compression engine to deep sub-micron technology provides substantial power and chip area benefits, while CMOS image sensor retains reliability with less advanced 180nm process. The dissertation concludes that 3D heterogeneous integration can increase power/performance efficiency of an image sensor system, but die-to-die thermal coupling may provide challenges in managing the quality of the compressed images.