Design, fabrication, and reliability study of second-level compliant microelectronic interconnects
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Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect reliability. The geometry of the compliant interconnect, its dimensions, and the material and processes used for fabricating the interconnect influence its mechanical and electrical characteristics, fabrication and assembly yield, thermo-mechanical and drop-impact reliability, and cost of fabrication. Although studies have examined various compliant interconnect designs, a multi-objective and multi-physics design optimization of the compliant interconnect has not been adequately pursued and implemented in prototypes. The first objective of this thesis is to develop a second-level multi-path compliant interconnect for microelectronic systems by performing compliance analysis and multi-physics design optimization using analytical and numerical models; The second objective of this thesis is to develop dry-film based sequential processes to fabricate such compliant interconnects on a silicon wafer, and to assemble singulated silicon substrates on organic printed circuit boards. In particular, in this work, the fabricated interconnects form a 45 × 45 array on the 18 mm × 18 mm silicon substrate. Several variations of the interconnects have been fabricated with the arcuate beam having a width of 10, 15, and 20µm on a footprint of 280µm, and with a pitch of 400µm. The third objective of this work is to experimentally demonstrate the thermal cycling reliability of the assemblies, and to validate the results from numerical models. The fourth objective is to experimentally demonstrate that compliant interconnects can effectively isolate the silicon substrate from the board under drop impact conditions, and to determine the reliability of the interconnects under drop impact conditions. It is seen that the compliant interconnects are able to isolate the silicon substrate from the board, and the board-to-substrate strain ratios are 21.55, 9.53 and 7.01 for compliant interconnects with arcuate beam width equal to 10μm, 15μm and 20μm, respectively, compared to 2.46 for solder ball interconnects. The experimental drop impact results are used for validating the drop-impact simulation predictions. Overall, by combining cleanroom fabrication, assembly, thermal cycling and drop-impact testing with analytical and numerical models as well as design optimization, this work provides a comprehensive insight into the development of multi-path copper structures as second-level microsystem interconnects.