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dc.contributor.authorTrivedi, Amit R.
dc.date.accessioned2017-01-11T13:57:17Z
dc.date.available2017-01-11T13:57:17Z
dc.date.created2015-12
dc.date.issued2015-10-06
dc.date.submittedDecember 2015
dc.identifier.urihttp://hdl.handle.net/1853/56178
dc.description.abstractThis dissertation explores cohesive design methodologies integrating emerging computing technologies/paradigms and computing applications. At first the limitations of conventional technology CMOS-based digital designs are mitigated by employing neuron learning-inspired circuit modules. It is shown that a limited switching slope of CMOS-based transistors constrains the energy-efficiency of CMOS-based digital computing. A power-gating efficiency leaner is discussed which is inspired by the neuronal learning principles. The power-gating efficiency learner optimally configuring the digital logic-block to power-gated or non power-gated mode, and mitigates limited switching slope-induced leakage power dissipation. The learner circuit is area and power-effective and facilitates adaptation against history and process/temperature conditions. A test-chip in IBM 130 nm process demonstrated the functionality of the learner circuit. Furthermore, for the emerging ultra low power image processing and associative memory applications, the dissertation has explored co-design of emerging tunneling field-effect-transistors (TFET) and large scale cellular neural network (CNN). Particularly, low ON/OFF current of Si channel TFET, while not promising for digital applications, is found suitable for large scale CNN. By collective computing, large scale CNN mitigates on-current deficiencies of Si channel TFET. Low ON current and subthermal slope of Si channel TFET operates a large scale CNN under lower power. While co-designing TFET and CNN-based associative memory, a higher neighborhood radius CNN exploits peculiar decreasing switching slope of TFET to enhance energy-efficiency of associative computing. Although, at lower power the variability of CNN computing elements aggravates; a higher neighborhood radius architecture averages and negates imperfections and mitigates variability challenges. Thereby, a co-design of TFET and CNN achieves higher energy efficiency and reliability even at lower power. Finally, the dissertation postulates non-conventional transistor designs for non-Boolean computing. It is shown that the exotic characteristics of non-conventional transistors can be harnessed by non-Boolean platforms to enhance their energy-efficiency. Particularly, a source/gate overlap heterojunction TFET (SO-HTFET) design was demonstrated to exhibit a unique negative gate transconductance (NGT) characteristic. This NGT characteristic of TFET realized associative processing non-Boolean cell with a single transistor. Thereby, a co-designed computing device presented exciting opportunities of compact and high memory capacity non-Boolean pattern matching.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subjectTunnel FET
dc.subjectNon Boolean computing
dc.subjectUltra low power computing
dc.subjectPower gating
dc.subjectProcess induced variability
dc.subjectAssociative processing
dc.subjectCellular neural network
dc.subjectImage processing
dc.subjectAssociative memory
dc.subjectOxygen vacancy
dc.subjectThree dimensional integration
dc.titleUltra low power non-Boolean computing with tunneling field-effect-transistors
dc.typeDissertation
dc.description.degreePh.D.
dc.contributor.departmentElectrical and Computer Engineering
thesis.degree.levelDoctoral
dc.contributor.committeeMemberMukhopadhyay, Saibal
dc.contributor.committeeMemberRaychowdhury, Arijit
dc.contributor.committeeMemberNaeemi, Azad
dc.contributor.committeeMemberYalamanchili, Sudhakar
dc.contributor.committeeMemberKim, Hyesoon
dc.date.updated2017-01-11T13:57:17Z


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