CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS
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The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D IC technologies refer to many vertical integration methodologies (such as through-silicon vias and face-to-face bumps) that enable the stacking of ICs. By 3D IC stacking, various benefits in terms of power and performance can be gained. However, it is not only the 3D IC design itself but also the design of the package and its many connections that must be optimized to maximize the benefit of 3D IC technology. Therefore, this work proposes design methodologies that enable reliable 3D IC in terms of signal integrity, power integrity, and thermal optimization.