CAD tools and methodologies for reliable 3D IC design, analysis, and optimization
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As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC systems with high performance and low power consumption is a challenging task. It is difficult to deliver power to all chips with a reduced footprint. And new parasitic elements in 3D ICs require accurate parasitic extraction and detailed design analysis in the full-chip level. The objective of this research is to quantify power and signal integrity issues in 3D ICs, and develop CAD tools and methodologies to enable reliable 3D IC designs, as well as enhance physical design quality. This includes accurate parasitic extraction, timing, power analysis, and signal-power-thermal integrity analysis and optimization for both face-to-back and face-to-face bonded 3D ICs. To achieve this goal, CAD tools and methodologies for 3D IC design, analysis and optimization flows are implemented from multiple aspects of physical designs. In this work, first, a holistic CAD platform is proposed to address the need for accurate modeling and analyzing IR drop issues in a 3D DRAM system with several optimization methods from design, packaging and architectural policy perspective. Also, accurate extraction methods are proposed for TSV-to-TSV coupling parasitic extraction by using multi-TSV model and pattern-matching algorithm. Then, several noise-protection methods are proposed to alleviate signal coupling in 3D ICs. Further, a holistic and an in-context methodology are proposed for extraction of inter-die coupling parasitics in F2F 3D ICs with accuracy and complexity tradeoff comparisons. Last, multiple impacts from physical design and technology scaling are studied with our tool flow demonstrated on extraction of the next generation heterogeneous F2F 3D ICs.