Chip-last Embedded Interconnect Structures

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Date
9/17/2013Author
Liu, Fuhan
Kumbhat, Nitesh
Sundaram, Venkatesh
Tummala, Rao R.
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Show full item recordAbstract
The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.
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- Georgia Tech Patents [1761]