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    Stress Relieving Second Level Interconnect Structures And Methods Of Making The Same

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    Date
    3/3/2015
    Author
    Raj, Pulugurtha Markondeya
    Kumbhat, Nitesh
    Sundaram, Venkatesh V.
    Tummala, Rao R.
    Qin, Xian
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    Abstract
    Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.
    URI
    http://hdl.handle.net/1853/56965
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