Distributed Instruction Queue

Abstract

A distributed instruction queue (DIQ) in a superscalar microprocessor supports multi-instruction issue, decoupled data flow scheduling, out-of-order execution, register renaming, multi-level speculative execution, and precise interrupts. The DIQ provides distributed instruction shelving without storing register values, operand value copying, and result value forwarding, and supports in-order issue as well as out-of-order issue within its functional unit. The DIQ allows a reduction in the number of global wires and replacement with private-local wires in the processor. The DIQ's number of global wires remains the same as the number of DIQ entries and data size increases. The DIQ maintains maximum machine parallelism and the actual performance of the microprocessor using the DIQ is better due to reduced cycle time or more operations executed per cycle.